Mixing Integrator for Compact Electrochemical Impedance Spectroscopy

With the rapid development in the miniaturization and monolithic integration of electrochemical sensors with integrated microchips on semiconductor technology, the power and area efficiency of the instrumentation circuits have become an emerging interest. Electrochemical Impedance Spectroscopy (EIS) is an analytical technique widely used in electrochemistry to investigate the properties of materials and electrode reactions. A conventional frequency-response analyzer (FRA) is a powerful EIS measurement instrument composed of amplification, mixing, and low-pass filtering blocks. This paper presents a resetting timing scheme in an integrating amplifier with capacitive feedback for combining three functions into one circuit. The proposed method benefits from lower power consumption and reduced silicon area occupation, as well as eases the design complexity. The theoretical principle of timing selection is expressed in mathematical equations and verified by the circuit simulations

Area and Power Efficient Ultra-Wideband Transmitter Based on Active Inductor

This paper presents the design of an impulse radio ultra-wideband (IR-UWB) transmitter for low-power, short-range, and high-data rate applications such as high density neural recording interfaces. The IR-UWB transmitter pulses are generated by modulating the output of a local oscillator. The large area requirement of the spiral inductor in a conventional on-chip LC tank is overcome by replacing it with an active inductor topology. The circuit has been fabricated in a UMC CMOS 180 nm technology, with a die area of 0.012 mm2. The temporal width of the output waveform is determined by a pulse generator based on logic gates. The measured pulse is compliant with Federal Communications Commission (FCC) power spectral density limits and within the frequency band of 3-6 GHz. For the minimum pulse duration of 1 ns, the energy consumption of the design is 20 pJ per bit, while transmitting at a 200 Mbps data rate with an amplitude of 130 mV

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly relevant for the monitoring of heart failure and pulmonary hypertension patients. The BDC is made of a piezoresistive pressure sensor and a readout integrated circuit (IC) that comprises an instrumentation amplifier (IA) followed by an analog-to-digital converter (ADC). The proposed design spins both the bridge excitation and the ADC’s sampling input voltages simultaneously and exploits duty cycling to reduce the static power consumption of the bridge sensor and IA while cancelling the IA’s offset and 1/f noise at the same time. The readout IC has been designed and fabricated in a standard 180-nm CMOS process and achieves 8.4 effective number of bits (ENOB) at 1 kHz sampling rate while drawing 0.53 µA current from a 1.2 V supply. The BDC, built with the readout IC and a differential pressure sensor having 5 kΩ bridge resistances, achieves 0.44 mmHg resolution in a 270 mmHg pressure range at 1 ms conversion time. The current consumption of the bridge sensor by employing duty cycling is reduced by 99.8% thus becoming 0.39 µA from a 1.2 V supply. The total conversion energy of the pressure sensing system is 1.1 nJ, and achieves a figure-of-merit (FoM) of 3.3 pJ/conversion, which both represent the state of the art

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 μW and occupies 0.021 mm² per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we implement and combine advanced compressive sampling algorithms to reduce the power requirements of wireless telemetry. Moreover, we apply variable compression, to dynamically modify the device performance, based on the actual signal need. This paper presents an area-efficient adaptive system for wireless implantable devices, which dynamically reduces the power requirements yielding compression rates from 8× to 64×, with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of 230×235 μm and 200 × 190 μm, respectively, while consuming only 0.47 μW at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively

A Low Power On-Chip Class-E Power Amplifier For Remotely Powered Implantable Sensor Systems

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the required high inductance values which make the on-chip integration of the power amplifier difficult. The designed power amplifier is fully integrated in the remotely powered sensor system and fabricated in 0.18 mu m CMOS process. The power is transferred to the implantable sensor system at 13.56 MHz by using an inductively coupled remote powering link. The induced AC voltage on the implant coil is converted into a DC voltage by a passive full-wave rectifier. A voltage regulator is used to suppress the ripples and create a clean and stable 1.8 V supply voltage for the sensor and communication blocks. The data collected from the sensors is transmitted by on-off keying modulated low-power transmitter at 1.2 GHz frequency. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. An additional output network is used for the power amplifier which makes the integration of the power amplifier fully on-chip. The integrated power amplifier with 0.2 V supply voltage has a drain efficiency of 31.5% at -10 dBm output power for 50 Omega load. The measurement results verify the functionality of the power amplifier and the remotely powered implantable sensor system. The data communication is also verified by using a commercial 50 Omega chip antenna and has 600 kbps data rate at 1 m communication distance

A remotely powered fully integrated low power class-E power amplifier for implantable sensor systems

This paper presents a fully integrated low power class-E power amplifier and its integration to remotely powered sensor system. The on-chip 1.2 GHz power amplifier is implemented in 0.18 A mu m CMOS process with 0.2 V supply. The implantable system is powered by using an inductively coupled remote powering link at 13.56 MHz. A passive full-wave rectifier converts the induced AC voltage on the implant coil into a DC voltage. A clean and stable 1.8 V supply voltage for the sensor and communication blocks is generated by a voltage regulator. On-off keying modulated low-power transmitter at 1.2 GHz is used for the transmission of the data collected from the sensors. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. Compared to the conventional class-E power amplifiers, an additional network which reduces the on-chip area is used at the output of the power amplifier. The measurement results verify the functionality of the remotely powered implantable sensor system and the power amplifier. The integrated power amplifier provides -10 dBm output power for 50 Omega load with a drain efficiency of 31.5 %. The uplink data communication with a data rate of 600 kbps is established by using a commercial 50 Omega chip antenna at 1 m communication distance

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

This paper presents techniques for increasing communication data rates for OOK modulated signals in the case the carrier frequency is generated by a cross-coupled pair LC oscillator. The proposed circuitry completely turns off the transmitter during the transmission of "0" bit and oscillation occurs only when the data bit is "1" to reduce power consumption. The data bit controls the steady state bias current and the operation of the oscillator. The communication data rate is limited by the turn-on and turn-off time of the LC oscillator. In order to speed up the turn-on time of the oscillator, in addition to bias current, an extra current source is used during the build-up of the oscillator. The decay time of the oscillator when the data is switched from "1" to "0" is accelerated by shortening the inductor connections. The concept is demonstrated through the design of an LC VCO in 0.18 mu m CMOS technology. The LC oscillator is designed to oscillate in MedRadio band at 416 MHz frequency. Simulation results show that the proposed architecture shortens the turn-on time from 86.5 ns to 24 ns and the turn-off time from 101 ns to 5.93 ns. With the additional techniques, the maximum achievable communication data rate is increased by more than 6 times

Design and comparison of class-C and class-D power amplifiers for remotely powered systems

This paper presents the effect of coupling between the coils on the power amplifier efficiency and comparisons between the class-C and class-D performance for different coupling conditions. In remotely powered systems, the coupling of the coils can influence the reflected load impedance seen by the power amplifier. The appropriate power amplifier needs to be chosen to deliver the power efficiently for different load conditions. The study also discusses the advantages and drawbacks of designing the class-C and class-D amplifiers

All Wireless, 16-channel Epilepsy Control System with Sub-mu W/channel and Closed-loop Stimulation Using a Switched-Capacitor-Based Active Charge Balancing Method

An all wireless closed-loop stimulation system for epilepsy control is presented that generates charged-balanced programmable stimulation current pulses upon a seizure is detected. The proposed system has highly flexible stimulation parameters thanks to the proposed switched-capacitor-based charge balancer (SCCB). The proposed active charge balancer is able to generate both charge-balanced symmetric and asymmetric stimulation pulses without requiring additional charge balancing phase. The straightforward design of the SCCB consumes low silicon area and low power consumption (4.7 mu W). The proposed charge balancer has an accurate and safe performance with a maximum remaining voltage of 25 mV. Furthermore, the structure of multi-input single-output compressive sensing (MISOCS) block proposed in this paper, improves the detection quality. The seizure detector of the proposed system has a sensitivity of 100% and false alarm rate of 0.09/h. The proposed system is implemented and validated using a 0.18 mu m technology